1. Field of the Invention
This invention relates to fault tolerant circuit arrangements, and is concerned more particularly, but not exclusively, with fault tolerant thin film transistor (TFT) circuits which may be used, for example, in drive and control circuits for active matrix liquid crystal displays (AMLCDs).
2. Description of the Related Art
A typical active matrix display device incorporates drive and control circuits at the periphery of the display area, which process the incoming information and provide it to the active display matrix. Typically, the display matrix is similar to a DRAM structure having column lines which carry data in the form of voltages and row lines to which timing signals are applied to control switching of pixel switching elements located at the intersections of the column lines and the row lines. The function of the pixel switching elements is to pass data voltages to a pixel capacitor in order to modulate some property of the display material.
The most common form of active matrix display is the AMLCD. In this form of display, the voltage stored at the pixel is used to modulate the optical properties of a thin layer of liquid crystal material.
Conventionally, the pixel switching elements in such a display are amorphous silicon thin film transistors (aSi-TFT), and the peripheral drive and control circuits are custom integrated circuits fabricated from single crystal silicon, bonded around the edge of the display and connected to the data and scan lines of the active matrix (which correspond to the above-mentioned column lines and row lines, respectively). In recent years, however, there has been a growing interest in the use of polysilicon thin film transistors fabricated at temperatures which are low enough to enable them to be integrated with the glass substrates used for the display. Polysilicon thin film transistors have sufficient performance to enable the peripheral drive and control circuits to be fabricated on the substrates with consequent benefits in terms of manufacturing cost and pixel pitch.
However, such integration of the drive and control circuits can result in a decrease in the manufacturing yield caused by faults within the integrated drive and control circuits. Furthermore, such circuits are prone to failure as a result of their large area and inherent variation in the properties of the thin film transistors, and a fault in one of the transistors could cause catastrophic failure of the whole panel. Variations in parameters, such as the threshold voltage and mobility of the transistors, often manifest themselves as a soft failure caused by the inability of a particular transistor to match the performance of neighboring transistors in the same circuit.
For these reasons, fault tolerant circuit design is becoming increasingly important, both in AMLCD applications in order to increase the yield of the displays with integrated drive circuitry, and also in other large area applications of thin film electronics.
A number of fault tolerant design techniques are already known.
A redundancy-with-repair (RWR) technique involves duplicating the basic functional circuit and employing some means to effect a repair if one of the functional circuits is found to be faulty after manufacture. For example, U.S. Pat. No. 5,111,060, and Y.Takafuji et al., SID'93 Digest, pages 383-386 disclose the application of an RWR technique to AMLCDs.
Furthermore, FIG. 1 of the accompanying drawings shows a RWR circuit arrangement for the peripheral circuit of an AMLCD in which a number of basic functional circuits are duplicated to form shift register element pairs 1, 1a; 2, 2a; 3, 3a, etc. Specifically, in the RWR circuit arrangement of FIG. 1, the spare shift register elements 1, 2, 3, etc. are connected between the associated circuit input and output by means of welding pads 4 and 5 in parallel with the shift register elements 1a, 2a, 3a, etc. connected between the associated circuit input and output by means of cutting pads 6 and 7. Thus, there is provision for completely removing a defective shift register element, such as the element 1a, from the circuit by irradiating the cutting pads 6 and 7 with a laser, and welding in the replacement shift register element, such as the element 1, by means of the welding pads 4 and 5.
While the RWR technique can offer significant fault tolerance with reasonable overhead and negligible detrimental effect on circuit performance, there are many applications in which the low level test and repair steps of such a technique are too expensive to incorporate in the fabrication process. Furthermore, it is preferred that fault tolerance should be provided without the need for repair of the circuit.
A triple-modular-redundance (TMR) technique involves, as shown diagrammatically in FIG. 2 of the accompanying drawings, replicating the basic functional circuit in triplicate and connecting the outputs of the circuits 10, 11 and 12 to a common voting circuit 13 for producing an output corresponding to the majority vote of the outputs of the circuits 10, 11 and 12. Such a technique is known, for example, from C.Bolchini et al., IEEE International Symposium on Circuits and Systems 1994, pages 83-86; and A. A.Sorenson: "Digital circuit reliability through redundancy", Electro-Technology, Vol.67, No.7, pages 118-125 (July-1961).
It will be appreciated that such a technique can be implemented by connecting the circuits 10, 11 and 12 to three AND gates driving a common OR gate. Such an arrangement is tolerant to a fault in any one of the three circuits 10, 11 and 12.
However, there is only a certain probability that such an arrangement will tolerate additional faults. Furthermore, the technique is rendered costly by the provision of circuits in triplicate and by the associated decision logic. Furthermore, the performance will be considerably inferior to a correctly functioning non-redundant circuit in terms of power consumption and speed, as a result of the additional load presented by the three parallel circuits and also the delay through the decision logic. For these reasons, the TMR technique is not practicable for the decision circuits of AMLCDs which are essentially simple replicated circuits required to operate at high speed.
Another technique which has not received as much attention in the literature is a Quad-Masking (QM) technique, as referred to in R. Kuehn: "Computer redundancy: design, performance and future", IEEE Transactions on Reliability, Vol.R-18, No.1, pages 3-11.
As shown diagrammatically in FIG. 3 of the accompanying drawings, the QM technique involves connecting together four basic functional circuits 15, 16, 17 and 18 such that the circuits 15 and 16 are in series and the circuits 17 and 18 are in series. The circuit pairs 15, 16 and 17, 18 are connected in two parallel paths between a common input and output. Such a technique is considerably more robust than the TMR technique, and at least two of the circuits must fail to cause failure of the arrangement.
The connection 19 shown by a broken line in FIG. 3 can be made according to the relative probabilities of occurrence of stuck open (non-conducting) and stuck closed (conducting) faults. If the arrangement is more likely to suffer from stuck open faults, the connection 19 is made since it gives another path through the arrangement. On the other hand, the connection 19 is not made if the arrangement is more likely to suffer from stuck closed faults. It does not matter whether or not the connection 19 is made if either type of fault is equally likely.
Although this technique is very robust, with only a modest area required for thin film MOS implementation, a circuit arrangement constructed with this type of logic will be slower and will exhibit a higher power consumption than its non-redundant counterpart.